Table of contents
This page will show the hardware and software requirements needed for enabling PCIe endpoint on the ESPRESSObin board.
1. Use a prebuilt PCIe x1 male to male crossover cable or modify PCIe x1 lane cable. Note that this cable MUST NOT have clock and power signals connected, otherwise you could damage your ESPRESSObin board. Consult the image below:
2. Use a mini-PCIe to PCIe adapter (image below) to bring out the PCIe x4 connector on the ESPRESSObin. It is important that this adapter is used in order to avoid overdriving PCIe voltage rails between two systems.
3. Connect one end of the crossover PCIe male to PCIe male cable to the mini-PCIe connector board and the other end to the host system board.
1. Modify the U-Boot code (for setting up U-Boot see Build From Source - Bootloader) to disable PCIe root complex mode and PCIe 100MHz clock outputs:
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 1bb321a..2701576 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -239,7 +239,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) * 6. Enable the output of 100M/125M/500M clock */ reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE), - 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); + 0xA00D | rb_clk500m_en , 0xFFFF); /*
2. Make sure to also comment out the following two lines from the drivers/pci/pcie_advk.c file as shown in the snippet (lines 483-484) below:
/* Set PCI global control register to RC mode */ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); //reg |= (IS_RC_MSK << IS_RC_SHIFT); //advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
3. Now build a new flash_image (as shown in Build from source - Bootloader) to program into the PCIe endpoint device, and flash the image as instructed in Update the Bootloader. You can download a prebuilt image for A3720-DB Marvell board by clicking here.
4. Lastly, power on the ESPRESSObin board and check for PCIe endpoint devices in the U-Boot prompt using the pci command. For example:
Marvell>> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x1b4b 0x0100 Mass storage controller 0x04